1. Field of the Invention
The present invention relates to a depletion MOS transistor and an enhancement MOS transistor.
2. Description of the Related Art
Conventionally known semiconductor memory devices include an electrically programmable nonvolatile type. In particular, NAND flash memories in which a plurality of memory cells are connected together in series to form a NAND cell are commonly used because these memories can be highly integrated.
Each memory cell in a NAND flash memory has a MOSFET structure in which a floating gate (charge accumulation layer) and a control gate are stacked on a semiconductor substrate with an insulating film interposed therebetween. A plurality of memory cells are connected together in series such that the adjacent memory cells share the source or drain. The memory cells thus form a NAND cell connected to a bit line as one unit. Such NAND cells are arranged in a matrix so as to form a memory cell array. Memory cell arrays are integrally formed on a p-type semiconductor substrate or in a p-type well region.
In the NAND flash memory, a voltage higher than a power supply voltage needs to be transferred to a control gate line in a selected block. To transfer such a high voltage to memory cells, the conventional NAND flash memory includes a row decoder circuit with a voltage conversion circuit configured to convert the power supply voltage into a high voltage. Such a configuration is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-196061. Such a row decoder generally includes plural types of MOS transistors such as a high breakdown-voltage enhancement-type (E-type) n-channel MOS transistor, a high breakdown-voltage depletion-type (D-type) re-channel MOS transistor, and a high breakdown-voltage E-type p-channel MOS transistor.
Thus, it is important that these high breakdown-voltage MOS transistors offer sufficient breakdown-voltages.